The present embodiments relate to integrated circuit designs and, more particularly, to simulation models of intellectual property cores (IP cores) or IP blocks that are implemented in integrated circuits such as programmable logic devices (PLDs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs) or graphic processing units (GPUs). Some examples of PLDs include programmable logic arrays (PLAs), programmable array logic (PAL), generic array logic (GAL), complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs).
A circuit design that is implemented with an integrated circuit typically includes various IP cores. IP cores could be provided as data (i.e., so-called soft IP cores) or as a circuit block (i.e., so-called hard IP cores or hard IP blocks). The 100G Interlaken IP core and the 100G Ethernet IP core are examples for soft IP cores provided by PLD vendors, while transceivers, memory controllers, or digital signal processors (DSPs) are examples for hard IP blocks in PLDs. IP cores provide various benefits. For example, the reuse of previously developed IP blocks shortens the development cycle of new applications. It is very common to provide simulation models with the IP cores, for example at the Register Transfer Level (RTL) to test and verify the behavior of the IP block with the remainder of the circuit design, before the circuit design is implemented with the integrated circuit.